1. Field of the Invention
The present invention relates to a semiconductor storage device, and more specifically to a semiconductor storage device having a plurality of banks therein.
2. Description of the Prior Art
Described below is a conventional semiconductor storage device having a plurality of banks. FIG. 9 shows the arrangement of the circuit of the conventional semiconductor storage device including an upper A bank, a lower B bank, and memory cells distributed to a plurality of banks. A circuit (hereinafter referred to an SAPN circuit) for driving the source node of a sense amplifier to perform a reading/rewriting operation on the memory cell of each bank is provided between the banks. FIG. 7 shows the connection of the circuit of the semiconductor storage device. FIG. 8 is a timing chart showing the operation of the circuit shown in FIG. 7.
In FIG. 7, a memory cell area (1) of an A bank is arranged at an upper portion while a memory cell area (15) of a B bank is arranged at a lower portion. The memory cell area (1) of the A bank contains a memory cell (2) and a cell transistor (3) connecting the memory cell (2) with a first bit line (5). A word line (4) is connected to the gate of a cell transistor (3). The first bit lines (5) and second bit lines (6) are connected to a sense amplifier (7) for amplifying the difference in electric potential between the bit lines. The Pch source electric potential and the Nch source electric potential of the sense amplifier (7) are provided from an SAP output Pch transistor (11) and an SAN output Nch transistor (12) provided below the memory cell area (1) through an SAP wiring (9) and an SAN wiring (8). The gates of the SAP output Pch transistor (11) and the SAN output Nch transistor (12) are controlled by an SE signal (14). There also is a similar element group of the configuration in the lower B bank.
In the circuit shown in FIG. 7, the source nodes of the SAP output Pch transistor (11) of the A bank and an SAP output transistor (25) of the B bank are connected to the same VDD wiring (41), while the source nodes of the SAN output Nch transistor (12) of the A bank and an SAN output transistor (26) of the B bank are connected to the same GND wiring (42).
Normally, in a semiconductor storage device having multiple banks, there is a timing at which a sense amplifier in a bank is in an active state while another bank is performing a sensing operation. Furthermore, there is a timing at which a word line of a bank is in an inactive state while another bank is performing a sensing operation. However, it is not allowed in a normal operation mode that a plurality of banks simultaneously set the sense amplifiers in the active state.
The operation of the circuit is explained below by referring to the timing chart shown in FIG. 8. The number preceded by t in, for example, t8-1 indicating a time point refers to the number of a figure, and the number preceded by the hyphen refers to the occurrence order of a corresponding point. At time point t8-1, the word line (4) of the A bank is set in the active state. When the electric potential stored in a memory cell indicates a high level, the electric potential of the first bit line (5) rises if the word line is set in the active state. At this time, a small potential difference occurs between the first bit lines (5) and second bit lines (6). At time point t8-2, when the SE signal (14) indicates a high level and the signals in the SAP and SAN wirings are set in the active state, the sense amplifier (7) starts its operation. Through the sensing operation, the potential difference between the first bit lines (5) and second bit lines (6) is amplified, the electric potential of the first bit line (5) is transmitted and rewritten to the memory cell (2). Thus, the data reading and rewriting operations of the memory cell are completed. However, when the sense amplifier is in the active state, an electric charge is provided for a number of bit lines, thereby generating a large noise in the VDD wiring (41) and the GND wiring (42).
In the above-described operations, the sense amplifier in the B bank has been set in the inactive state. At time t8-3, the word line of the B bank enters the active state. As in the A bank, the SE signal of the B bank enters the active state at time t8-4, and the sensing operation starts. The sensing operation generates a sense noise in the VDD wiring (41) and the GND wiring (42). Since the A and B banks share the source of the SAP and SAN output transistor, the sense noise is also transmitted to the SAP wiring (9) and the SAN wiring (8) of the A bank, thereby reducing the electric potential of the first bit line (5) and of the memory cell (2). At this time, when the word line (4) of the A bank indicates a low level at time t8-5, the memory cell (2) is disconnected from the first bit line (5) with the amount of the electric charge reduced by the sense noise in another bank, thereby possibly generating a problem of, for example, an error read in the subsequent reading operation, etc.
To solve the above-described problem, each bank is provided with VDD wirings (45 and 47) and GND wirings (46 and 48) for providing an electric current for the SAP output Pch transistor and the SAN output Nch transistor for each bank to which the SAP wiring and the SAN wiring are connected respectively as shown in FIG. 5 according to the conventional technology. As shown in the timing chart shown in FIG. 6, a sense noise is generated in the VDD wiring (47) and the GND wiring (48) for the B bank at time t6-4 even when the operation is performed at the similar timing as shown in FIG. 8. However, since the VDD wiring (45) and the GND wiring (46) for the A bank have no influences, the electric charge stored in the memory cell (2) is not affected by the noise, and the word line for the A bank enters the inactive state at time point t6-5.